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ai02065 18 a0-a17 w dq0-dq14 v cc M29W400t M29W400b e v ss 15 g rp dq15a1 byte rb figure 1. logic diagram M29W400t M29W400b 4 mbit (512kb x8 or 256kb x16, boot block) low voltage single supply flash memory not for new design M29W400t and M29W400b are replaced respectively by the M29W400bt and M29W400bb 2.7v to 3.6v supply voltage for program, erase and read operations fast access time: 90ns fast programming time 10 m s by byte / 16 m s by word typical program/erase controller (p/e.c.) program byte-by-byte or word-by-word status register bits and ready/busy output memory blocks boot block (top or bottom location) parameter and main blocks block, multi-block and chip erase multi block protection/temporary unprotection modes erase suspend and resume modes read and program another block during erase suspend low power consumption stand-by and automatic stand-by 100,000 program/erase cycles per block 20 years data retention defectivity below 1ppm/year electronic signature manufacturer code: 0020h device code, M29W400t: 00eeh device code, M29W400b: 00efh description the M29W400 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a byte-by-byteor word- by-word basis using only a single 2.7v to 3.6v v cc supply. for program and erase operations the necessary high voltages are generated internally. the device can also be programmed in standard programmers. the array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. blocks can be protected against pro- graming and erase on programming equipment, november 1999 1/34 this is information on a product still in productionbut not recommended for new designs. 44 1 so44 (m) tsop48 (n) 12 x 20 mm bga fbga48 (za) 8 x 6 solder balls
dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15a1 v cc dq4 dq5 a7 dq7 nc nc ai02066 M29W400t M29W400b (normal) 12 1 13 24 25 36 37 48 dq8 nc nc a1 nc a4 a5 dq1 dq11 g a12 a13 a16 a11 byte a15 a14 v ss e a0 rp v ss figure 2a. tsop pin connections g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 byte dq15a1 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 w rb a4 nc rp a7 ai02068 M29W400t M29W400b 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 a17 a8 figure 2c. so pin connections dq3 dq9 dq2 dq0 dq6 dq13 dq14 dq12 dq10 dq15a1 v cc dq4 dq5 dq7 ai02067 M29W400t M29W400b (reverse) 12 1 13 24 25 36 37 48 dq8 dq1 dq11 a16 byte v ss a0 v ss a6 a3 a8 a9 a17 a10 a2 a7 nc nc nc nc a1 nc a4 a5 a12 a13 a11 a15 a14 rp w rb g e figure 2b. tsop reverse pin connections a0-a17 address inputs dq0-dq7 data input/outputs, command inputs dq8-dq14 data input/outputs dq15a1 data input/output or address input e chip enable g output enable w write enable rp reset / block temporary unprotect rb ready/busy output byte byte/word organisation v cc supply voltage v ss ground table 1. signal names warning: nc = not connected. warning: nc = not connected. warning: nc = not connected. 2/34 M29W400t, M29W400b
symbol parameter value unit t a ambient operating temperature (3) 40 to 85 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2) input or output voltages 0.6 to 5 v v cc supply voltage 0.6 to 5 v v (a9, e, g, rp) (2) a9, e, g, rp voltage 0.6 to 13.5 v notes: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to 2v during transition and for less than 20ns. 3. depends on range. table 2. absolute maximum ratings (1) description (cont'd) ai00912 d e f 8 7 6 5 4 3 2 1 b c a v ss dq15 a1 a15 a14 a12 a13 dq3 dq11 dq10 nc nc rb dq1 dq9 dq8 dq0 a6 a17 a7 g e a0 a4 a3 dq2 dq6 dq13 dq14 a10 a8 a9 dq4 v cc dq12 dq5 nc nc rp w a11 dq7 a1 a2 v ss a5 nc a16 byte figure 2d. fbga package ball out (top view) warning: nc = not connected. and temporarily unprotected to make changes in the application. each block can be programmed and erased over 100,000 cycles. instructions for read/reset, auto select for read- ing the electronic signature or block protection status, programming, block and chip erase, erase suspend and resume are written to the device in cycles of commands to a command interface using standard microprocessor write timings. the device is offered in tsop48 (12 x 20mm), so44 and fbga48 (8 x 6 balls, 0.8mm pitch) packages. both normal and reverse pinouts are available for the tsop48 package. 3/34 M29W400t, M29W400b
16k boot block ai02090 7ffffh 7c000h 7bfffh 7a000h 79fffh 40000h 3ffffh 8k parameter block 8k parameter block 32k main block 64k main block 64k main block 64k main block 20000h 1ffffh 10000h 0ffffh 00000h M29W400t 64k main block 64k main block 64k main block 78000h 77fffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh M29W400b 16k boot block 8k parameter block 8k parameter block 32k main block 64k main block 64k main block 64k main block 64k main block 64k main block 64k main block 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 7ffffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 10000h 0ffffh 08000h 07fffh 04000h 03fffh 00000h 64k main block 06000h 05fffh 64k main block 30000h 2ffffh figure 3. memory map and block address table (x8) organisation the M29W400 is organised as 512k x8 or 256k x16 bits selectable by the byte signal. when byte is low the byte-wide x8 organisation is selected and the address lines are dq15a1 and a0-a17. the data input/output signal dq15a1 acts as address line a1 which selects the lower or upper byte of the memory word for output on dq0-dq7, dq8-dq14 remain at high impedance. when byte is high the memory uses the address inputs a0-a17 and the data input/outputs dq0- dq15. memory control is provided by chip enable e, output enable g and write enable w inputs. a reset/block temporary unprotection rp tri-level input provides a hardware reset when pulled low, and when held high (at v id ) temporarily unprotects blocks previously protected allowing them to be programed and erased. erase and programopera- tions are controlled by an internal program/erase controller (p/e.c.). status register data output on dq7 provides a data polling signal, and dq6 and dq2 provide toggle signals to indicate the state of the p/e.c operations. a ready/busy rb output indicates the completion of the internal algorithms. memory blocks the devices feature asymmetrically blocked archi- tecture providing system memory integration. both M29W400tand M29W400bdevices have an array of 11 blocks, one boot block of 16 kbytes or 8 kwords, two parameter blocks of 8 kbytes or 4 kwords, one main block of 32 kbytes or 16 kwords and seven main blocks of 64 kbytes or 32 kwords. the M29W400t has the boot block at the top of the memory address space and the M29W400b locates the boot block starting at the bottom. the memory maps are showed in figure 3. each block can be erased separately, any com- bination of blocks can be specified for multi-block erase or the entire chip may be erased. the erase operations are managed automatically by the p/e.c. the block erase operation can be sus- pended in order to read from or program to any block not being ersased, and then resumed. block protection provides additional data security. each block can be separately protected or unpro- tected against program or erase on programming equipment. all previously protected blocks can be temporarily unprotected in the application. 4/34 M29W400t, M29W400b
address range (x8) address range (x16) a17 a16 a15 a14 a13 a12 00000h-03fffh 00000h-01fffh 00000x 04000h-05fffh 02000h-02fffh 000010 06000h-07fffh 03000h-03fffh 000011 08000h-0ffffh 04000h-07fffh 0001xx 10000h-1ffffh 08000h-0ffffh 0 0 1 x x x 20000h-2ffffh 10000h-17fffh 0 1 0 x x x 30000h-3ffffh 18000h-1ffffh 0 1 1 x x x 40000h-4ffffh 20000h-27fffh 1 0 0 x x x 50000h-5ffffh 28000h-2ffffh 1 0 1 x x x 60000h-6ffffh 30000h-37fffh 1 1 0 x x x 70000h-7ffffh 38000h-3ffffh 1 1 1 x x x table 3b. M29W400b block address table address range (x8) address range (x16) a17 a16 a15 a14 a13 a12 00000h-0ffffh 00000h-07fffh 0 0 0 x x x 10000h-1ffffh 08000h-0ffffh 0 0 1 x x x 20000h-2ffffh 10000h-17fffh 0 1 0 x x x 30000h-3ffffh 18000h-1ffffh 0 1 1 x x x 40000h-4ffffh 20000h-27fffh 1 0 0 x x x 50000h-5ffffh 28000h-2ffffh 1 0 1 x x x 60000h-6ffffh 30000h-37fffh 1 1 0 x x x 70000h-77fffh 38000h-3bfffh 1110xx 78000h-79fffh 3c000h-3cfffh 111100 7a000h-7bfffh 3d000h-3dfffh 111101 7c000h-7ffffh 3e000h-3ffffh 11111x table 3a. M29W400t block address table bus operations the following operations can be performed using the appropriate bus cycles: read (array, electronic signature, block protection status), write com- mand, output disable, standby, reset, block pro- tection, unprotection, protection verify, unprotec- tion verify and block temporary unprotection. see tables 4 and 5. 5/34 M29W400t, M29W400b
command interface instructions, made up of commands written in cy- cles, can be given to the program/erase controller through a command interface (c.i.). for added data protection, program or erase execution starts after 4 or 6 cycles. the first, second, fourth and fifth cycles are used to input coded cycles to the c.i. this coded sequence is the same for all pro- gram/erase controller instructions. the 'com- mand' itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. any incorrect command or any improper command se- quence will reset the device to read array mode. instructions seven instructions are defined to perform read array, auto select (to read the electronicsignature or block protection status), program, block erase, chip erase, erase suspend and erase resume. the internal p/e.c. automatically handles all tim- ing and verification of the program and erase operations. the status register data polling, tog- gle, error bits and the rb output may be read at any time, during programming or erase, to monitor the progress of the operation. instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interfacewhich is common to all instruc- tions (see table 8). the third cycle inputs the instruction set-up command. subsequent cycles output the addressed data, electronic signature or block protection status for read operations. in order to give additionaldata protection,the instruc- tions for program and block or chip erase require furthercommand inputs. for a programinstruction, the fourth command cycle inputs the address and data to be programmed. for an erase instruction (block or chip), the fourth and fifth cycles input a further coded sequence before the erase confirm command on the sixth cycle. erasure of a memory block may be suspended,in order to read data from another block or to program data in another block, and then resumed. when power is first applied or if v cc falls below v lko , the command interface is reset to read array. signal descriptions see figure 1 and table 1. address inputs (a0-a17) . the address inputs for the memory array are latched during a write opera- tion on the falling edge of chip enable e or write enable w. in word-wide organisation the address lines are a0-a17, in byte-wide organisation dq15a1 acts as an additional lsb address line. when a9 is raised to v id , either a read electronic signature manufacturer or device code, block protection status or a write block protection or block unprotection is enabled depending on the combination of levels on a0, a1, a6, a12 and a15. data input/outputs (dq0-dq7). these in- puts/outputs are used in the byte-wide and word- wide organisations. the input is data to be programmed in the memory array or a command to be written to the c.i. both are latched on the rising edge of chip enable e or write enable w. the output is data from the memory array, the electronic signature manufacturer or device codes, the block protection status or the status register data polling bit dq7, the toggle bits dq6 and dq2, the error bit dq5 or the erase timer bit dq3. outputs are valid when chip enable e and output enable g are active. the output is high impedance when the chip is deselected or the outputs are disabled and when rp is at a low level. data input/outputs (dq8-dq14 and dq15a1). these inputs/outputs are additionally used in the word-wide organisation.when byteis high dq8- dq14 and dq15a1 act as the msb of the data input or output, functioning as described for dq0- dq7 above, and dq8-dq15 are 'don't care' for command inputs or status outputs. when byte is low, dq8-dq14 are high impedance, dq15a1 is the address a1 input. chip enable (e). the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. e highdeselects the memory and reduces the power consumptionto the standby level. e can also be used to control writing to the command register and to the memory array, while w remains at a low level. the chip enable must be forced to v id during the block unprotection opera- tion. 6/34 M29W400t, M29W400b
output enable (g). the output enable gates the outputs through the data buffers during a read operation. when g is high the outputs are high impedance. g must be forced to v id level during block protection and unprotection operations. write enable (w). this input controls writing to the command register and addressand data latches. byte/word organization select (byte). the byte input selects the output configurationfor the device: byte-wide (x8) mode or word-wide (x16) mode. when byte is low, the byte-wide mode is selected and the data is read and programmed on dq0-dq7. in this mode, dq8-dq14 are at high impedance and dq15a1 is the lsb address. when byte is high, the word-wide mode is se- lected and the data is read and programmed on dq0-dq15. ready/busy output (rb). ready/busy is an open-drain output and gives the internal state of the p/e.c. of the device. when rb is low, the device is busy with a program or erase operation and it will not accept any additional program or erase instructions except the erase suspend instruction. when rb is high, the device is ready for any read, program or erase operation. the rb will also be high when the memory is put in erase suspend or standby modes. reset/block temporary unprotect input (rp). the rp input provides hardware reset and pro- tected block(s) temporary unprotection functions. reset of the memory is acheived by pulling rp to v il for at least t plpx . when the reset pulse is given, if the memory is in read or standby modes, it will be available for new operations in t phel after the rising edge of rp. if the memory is in erase, erase suspend or program modes the reset will take t plyh during which the rb signal will be held at v il . the end of the memory reset will be indicated by the rising edge of rb. a hardware reset during an erase or program operation will corrupt the data being programmed or the sector(s) being erased (see table 14 and figure 9). temporary block unprotection is made by holding rp at v id . in this condition previously protected blocks can be programmed or erased. the transi- tion of rp from v ih to v id must slower than t phphh . when rp is returned from v id to v ih all blocks temporarily unprotected will be again protected. see table 15 and figure 9. v cc supply voltage. the power supply for all operations (read, program and erase). v ss ground. v ss is the reference for all voltage measurements. device operations see tables 4, 5 and 6. read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register or the block protection status. both chip enable e and output enable g must be low in order to read the output of the memory. write. writeoperationsare used to give instruction commands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable e is low and write enable w is low with output enable g high. addresses are latched on the falling edge of w or e whichever occurs last. commands and inputdata are latchedon therising edge of w or e whichever occurs first. output disable. the data outputs are high imped- ance when the output enable g is high with write enable w high. standby. the memory is in standby when chip enable e is high and the p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable g or write enable w inputs. automatic standby. after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the cmos standby value, while outputs still drive the bus. electronic signature. two codes identifying the manufacturer and the device can be read from the memory. the manufacturer 's code for stmi- croelectronics is 20h, the device code is eeh for the M29W400t (top boot) and efh for the M29W400b(bottom boot). these codes allow pro- gramming equipment or applications to automat- ically match their interface to the characteristics of the M29W400. the electronic signature is output by a read operation when the voltage applied to a9 is at v id and address inputs a1 is low. the manufacturer code is output when the address input a0 is low and the device code when this input is high. other address inputs are ignored. the codes are output on dq0-dq7. the electronic signature can also be read, without raising a9 to v id , by giving the memory the instruc- tion as. if the byte-wide configuration is selected the codes are output on dq0-dq7 with dq8-dq14 at high impedance; if the word-wide configuration is selected the codes are output on dq0-dq7 with dq8-dq15 at 00h. 7/34 M29W400t, M29W400b
org. code device e g w byte a0 a1 other addresses dq15 a1 dq8- dq14 dq0- dq7 word- wide manufact. code v il v il v ih v ih v il v il don't care 0 00h 20h device code M29W400t v il v il v ih v ih v ih v il don't care 0 00h eeh M29W400b v il v il v ih v ih v ih v il don't care 0 00h efh byte- wide manufact. code v il v il v ih v il v il v il don't care don't care hi-z 20h device code M29W400t v il v il v ih v il v ih v il don't care don't care hi-z eeh M29W400b v il v il v ih v il v ih v il don't care don't care hi-z efh table 5. read electronic signature (following as instruction or with a9 = v id ) code e g w a0 a1 a12-a17 other addresses dq0-dq7 protected block v il v il v ih v il v ih block address don't care 01h unprotected block v il v il v ih v il v ih block address don't care 00h table 6. read block protection with as instruction operation e g w rp byte a0 a1 a6 a9 a12 a15 dq15 a1 dq8- dq14 dq0-dq7 read word v il v il v ih v ih v ih a0 a1 a6 a9 a12 a15 data output data output data output read byte v il v il v ih v ih v il a0 a1 a6 a9 a12 a15 address input hi-z data output write word v il v ih v il v ih v ih a0 a1 a6 a9 a12 a15 data input data input data input write byte v il v ih v il v ih v il a0 a1 a6 a9 a12 a15 address input hi-z data input output disable v il v ih v ih v ih x x x x x x x hi-z hi-z hi-z standby v ih xxv ih x x x x x x x hi-z hi-z hi-z reset x x x v il x x x x x x x hi-z hi-z hi-z block protection (2,4) v il v id v il pulse v ih xxxxv id xx x x x blocks unprotection (4) v id v id v il pulse v ih xxxxv id v ih v ih xxx block protection verify (2 ,4) v il v il v ih v ih xv il v ih v il v id a12 a15 x x block protect status (3) block unprotection verify (2 ,4) v il v il v ih v ih xv il v ih v ih v id a12 a15 x x block protect status (3) block temporary unprotection xx x v id x xxxxxx x x x notes: 1. x = v il or v ih 2. block address must be given on a12-a17 bits. 3. see table 6. 4. operation performed on programming equipment. table 4. user bus operations (1) 8/34 M29W400t, M29W400b
block protection. each block can be separately protected against program or erase on program- ming equipment. block protection provides addi- tional data security, as it disables all program or erase operations.this mode is activatedwhen both a9 and g are raised to v id and an address in the block is applied on a12-a17. the block protection algorithm is shown in figure 14. block protectionis initiated on the edge of w falling to v il . then after a delay of 100 m s, the edge of w rising to v ih ends the protection operations. block protection verify is achieved by bringing g, e, a0 and a6 to v il and a1 to v ih , while w is at v ih and a9 at v id . under these conditions, reading the data output will yield 01h if the block defined by the inputs on a12-a17 is protected. any attempt to program or erase a pro- tected block will be ignored by the device. block temporary unprotection. any previously protected block can be temporarily unprotected in order to change stored data. the temporary unpro- tection mode is activated by bringing rp to v id . during the temporary unprotection mode the pre- viously protected blocks are unprotected. a block can be selected and data can be modified by executing the eraseor program instruction with the rp signal held at v id . when rp is returned to v ih , all the previously protected blocks are again pro- tected. block unprotection. all protected blocks can be unprotected on programming equipment to allow updating of bit contents. all blocks must first be protected before the unprotectionoperation. block unprotection is activated when a9, g and e are at v id and a12, a15 at v ih . the block unprotection algorithm is shown in figure 15. unprotection is initiated by the edge of w fallingto v il . aftera delay of 10ms, the unprotection operation will end. un- protection verify is achieved by bringing g and e to v il while a0 is at v il , a6 and a1 are at v ih and a9 remains at v id . in these conditions, reading the output data will yield 00h if the block defined by the inputs a12-a17 has been succesfully unprotected. each block must be separatelyverified by giving its address in order to ensure that it has been unpro- tected. instructions and commands the command interface latches commands writ- ten to the memory. instructions are made up from one or more commands to perform read memory array, read electronic signature, read block pro- tection, program, block erase, chip erase, erase suspend and erase resume. commands are made of address and data sequences. the in- structions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the instruction. they are followed by either further write cycles to confirm the first command or execute the command immediately. command se- quencing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycles has been chosen to assure maximum data security. instructions are initialised by two initial coded cy- cles which unlock the command interface. in addi- tion, for erase, instruction confirmation is again preceded by the two coded cycles. hex code command 00h invalid/reserved 10h chip erase confirm 20h reserved 30h block erase resume/confirm 80h set-up erase 90h read electronic signature/ block protection status a0h program b0h erase suspend f0h read array/reset table 7. commands 9/34 M29W400t, M29W400b
mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rd (2,4) read/reset memory array 1+ addr. (3,7) x read memory array until a new write cycle is initiated. data f0h 3+ addr. (3,7) byte aaaah 5555h aaaah read memory array until a new write cycle is initiated. word 5555h 2aaah 5555h data aah 55h f0h as (4) auto select 3+ addr. (3,7) byte aaaah 5555h aaaah read electronic signature or block protection status until a new write cycle is initiated. see note 5 and 6. word 5555h 2aaah 5555h data aah 55h 90h pg program 4 addr. (3,7) byte aaaah 5555h aaaah program address read data polling or toggle bit until program completes. word 5555h 2aaah 5555h data aah 55h a0h program data be block erase 6 addr. (3,7) byte aaaah 5555h aaaah aaaah 5555h block address additional block (8) word 5555h 2aaah 5555h 5555h 2aaah data aah 55h 80h aah 55h 30h 30h ce chip erase 6 addr. (3,7) byte aaaah 5555h aaaah aaaah 5555h aaaah note 9 word 5555h 2aaah 5555h 5555h 2aaah 5555h data aah 55h 80h aah 55h 10h es (10) erase suspend 1 addr. (3,7) x read until toggle stops, then read all the data needed from any block(s) not being erased then resume erase. data b0h er erase resume 1 addr. (3,7) x read data polling or toggle bits until erase completes or erase is suspended another time data 30h notes: 1. commands not interpreted in this table will default to read array mode. 2. a wait of t plyh is necessary after a read/reset command if the memory was in an erase or program mode before starting any new operation (see table 14 and figure 9). 3. x = don't care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the command cycles. 5. signature address bits a0, a1 at v il will output manufacturer code (20h). address bits a0 at v ih and a1 at v il will output device code. 6. block protection address: a0 at v il ,a1atv ih and a12-a17 within the block will output the block protection status. 7. for coded cycles address inputs a15-a17 are don't care. 8. optional, additional blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through dq3 value (see erase timer bit dq3 description). when full command is entered, read data polling or toggle bit until erase is completed or suspended. 9. read data polling, toggle bits or rb until erase completes. 10.during erase suspend,read and data program functions are allowed in blocks not being erased. table 8. instructions (1) status register bits p/e.c. status is indicated during execution by data polling on dq7, detection of toggle on dq6 and dq2, or error on dq5 and erase timer dq3 bits. any read attempt during program or erase com- mand executionwill automaticallyoutput these five status register bits. the p/e.c. automatically sets bits dq2, dq3, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are reserved for future use and should be masked. see tables 9 and 10. data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. during erase operation, it outputs a '0'. after com- pletion of the operation,dq7 will output the bit last programmed or a '1' after erasing. data polling is valid and only effective during p/e.c. operation, 10/34 M29W400t, M29W400b
dq name logic level definition note 7 data polling '1' erase complete or erase block in erase suspend indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. '0' erase on-going dq program complete or data of non erase block during erase suspend dq program on-going 6 toggle bit '-1-0-1-0-1-0-1-' erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete '-1-1-1-1-1-1-1-' erase complete or erase suspend on currently addressed block 5 error bit '1' program or erase error this bit is set to '1' in the case of programming or erase failure. '0' program or erase on-going 4 reserved 3 erase time bit '1' erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es). '0' erase timeout period on-going an additional block to be erased in parallel can be entered to the p/e.c. 2 toggle bit '-1-0-1-0-1-0-1-' chip erase, erase or erase suspend on the currently addressed block. erase error due to the currently addressed block (when dq5 = '1'). indicates the erase status and allows to identify the erased block 1 program on-going, erase on-going on another block or erase complete dq erase suspend read on non erase suspend block 1 reserved 0 reserved notes: logic level '1' is high, '0' is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. table 9. status register bits that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be per- formed at the address being programmed or at an address within the block being erased. if all the blocks selected for erasure are protected, dq7 will be set to '0' for about 100 m s, and then return to the previous addressed memory data value. see fig- ure 11 for the data polling flowchart and figure 10 for the data polling waveforms. dq7 will also flag the erase suspend mode by switching from '0' to '1' at the start of the erase suspend. in order to monitor dq7 in the erase suspend mode an ad- dress within a block being erased must be pro- vided. for a read operation in erase suspend mode, dq7 will output '1' if the read is attempted on a blockbeing erasedand the data value on other blocks. during program operation in erase sus- pend mode, dq7 will have the same behaviour as in the normal program execution outside of the suspend mode. 11/34 M29W400t, M29W400b
toggle bit (dq6). when programming or erasing operations are in progress, successive attempts to read dq6 will output complementary data. dq6 will toggle following toggling of either g, or e when g is low. the operation is completed when two suc- cessive reads yield the same output data. the next read will output the bit last programmedor a '1'after erasing. the toggle bit dq6 is valid only during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. if the blocks selected for erasure are pro- tected, dq6 will toggle for about 100 m s and then return back to read. dq6 will be set to '1' if a read operation is attempted on an erase suspendblock. when erase is suspended dq6 will toggle during programming operations in a block different to the block in erase suspend. either e or g toggling will cause dq6 to toggle. see figure 12 for toggle bit flowchart and figure 13 for toggle bit waveforms. toggle bit (dq2). this toggle bit, together with dq6, can be used to determine the device status during the erase operations.it can also be used to identify the block being erased. during erase or erase suspend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will set dq2 to '1' during erase and to dq2 during erase suspend. during chip erase a read operation will cause dq2 to toggle as all blocks are being erased. dq2 will be set to '1' during program operation and when erase is com- plete. after erase completion and if the error bit dq5 is set to '1', dq2 will toggle if the faulty block is addressed. error bit (dq5). this bit is set to '1' by the p/e.c. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. in caseof an errorin block erase or program, the block in which the error occured or to which the programmed data belongs, must be discarded. the dq5 failure condition will also ap- pear if a user tries to program a '1' to a location that is previously programmed to '0'. other blocks may stillbe used. the errorbit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to '0' . erase timer bit (dq3). this bit is set to '0' by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the erase timeout period is finished, after 50 m sto90 m s, dq3 returns to '1'. coded cycles the two coded cycles unlock the command inter- face. they are followed by an input command or a confirmation command. the coded cycles consist of writing the data aah at address aaaah in the byte-wide configuration and at address 5555h in the word-wide configuration during the first cycle. during the second cycle the coded cycles consist of writing the data 55h at address 5555h in the byte-wide configuration and at address 2aaah in the word-wide configuration.in the byte-wide con- figurationthe address lines a1 to a14 are valid, in word-wide a0 to a14 are valid, other address lines are 'don't care'. the coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. instructions see table 8. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionallyprecededby the two coded cycles. subsequentread operationswill read the memory array addressed and output the data read. a wait state of 10 m s is necessary after read/reset prior to any valid read if the memory was in an erase mode when the rd instruction is given. auto select (as) instruction. this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address aaaah in the byte-wide configuration or address 5555h in the word-wide configuration for command set-up. a subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of a0 and a1. the manufacturer code, 20h, is output when the ad- dresses lines a0 and a1 are low, the device code, eeh for top boot, efh for bottom boot is output when a0 is high with a1 low. the as instruction also allows access to the block protectionstatus.aftergiving the as instruction, a0 is set to v il with a1 at v ih , while a12-a17 define the address of the block to be verified. a read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle note 1 erase suspend read (in erase suspend block) 1 1 toggle erase suspend read (outside erase suspend block) dq7 dq6 dq2 erase suspend program dq7 toggle n/a note: 1. toggle if the address is within a block being erased. '1' if the address is within a block not being erased. table 10. polling and toggle bits 12/34 M29W400t, M29W400b
symbol parameter test condition min max unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf note: 1. sampled only, not 100% tested. table 12. capacitance (1) (t a =25 c, f = 1 mhz ) ai01417 3v 0v 1.5v figure 4. ac testing input output waveform ai01968 0.8v out c l = 30pf or 100pf c l includes jig capacitance 3.3k w 1n914 device under test figure 5. ac testing load circuit input rise and fall times 10ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v table 11. ac measurement conditions symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 supply current (read) byte e = v il ,g=v ih , f = 6mhz 10 ma i cc1 supply current (read) word e = v il ,g=v ih , f = 6mhz 10 ma i cc3 supply current (standby) e = v cc 0.2v 50 m a i cc4 (1) supply current (program or erase) byte program, block or chip erase in progress 20 ma v il input low voltage 0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.3 v v ol output low voltage i ol = 4ma 0.45 v v oh output high voltage cmos i oh = 100 m av cc 0.4v v v id a9 voltage (electronic signature) 11.0 12.0 v i id a9 current (electronic signature) a9 = v id 100 m a v lko supply voltage (erase and program lock-out) 2.0 2.3 v note: 1. sampled only, not 100% tested. table 13. dc characteristics (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c; v cc = 2.7v to 3.6v) 13/34 M29W400t, M29W400b
symbol alt parameter test condition M29W400t / M29W400b unit -90 -100 v cc = 3.0v to 3.6v c l = 30pf v cc = 2.7v to 3.6v c l = 30pf min max min max t avav t rc address valid to next address valid e=v il , g=v il 90 100 ns t avqv t acc address valid to output valid e=v il , g=v il 90 100 ns t elqx (1) t lz chip enable low to output transition g=v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 90 100 ns t glqx (1) t olz output enable low to output transition e=v il 00ns t glqv (2) t oe output enable low to output valid e = v il 35 40 ns t ehqx t oh chip enable high to output transition g=v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 30 30 ns t ghqx t oh output enable high to output transition e=v il 00ns t ghqz (1) t df output enable high to output hi-z e = v il 30 30 ns t axqx t oh address transition to output transition e=v il , g=v il 00ns t plyh (1,3) t rrb t ready rp low to read mode 10 10 m s t phel t rh rp high to chip enable low 50 50 ns t plpx t rp rp pulse width 500 500 ns t elbl t elbh t elfl t elfh chip enable to byte switching low or high 55ns t blqz t flqz byte switching low to output high z 50 50 ns t bhqv t fhqv byte switching high to output valid 50 50 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . 3. to be considered only if the reset pulse is given while the memory is in erase or program mode. table 14a. read ac characteristics (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) 14/34 M29W400t, M29W400b
symbol alt parameter test condition M29W400t / M29W400b unit -120 -150 v cc = 2.7v to 3.6v v cc = 2.7v to 3.6v min max min max t avav t rc address valid to next address valid e=v il , g=v il 120 150 ns t avqv t acc address valid to output valid e=v il , g=v il 120 150 ns t elqx (1) t lz chip enable low to output transition g=v il 00ns t elqv (2) t ce chip enable low to output valid g = v il 120 150 ns t glqx (1) t olz output enable low to output transition e=v il 00ns t glqv (2) t oe output enable low to output valid e = v il 50 55 ns t ehqx t oh chip enable high to output transition g=v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 30 40 ns t ghqx t oh output enable high to output transition e=v il 00ns t ghqz (1) t df output enable high to output hi-z e = v il 30 40 ns t axqx t oh address transition to output transition e=v il , g=v il 00ns t plyh (1,3) t rrb t ready rp low to read mode 10 10 m s t phel t rh rp high to chip enable low 50 50 ns t plpx t rp rp pulse width 500 500 ns t elbl t elbh t elfl t elfh chip enable to byte switching low or high 55ns t blqz t flqz byte switching low to output high z 60 60 ns t bhqv t fhqv byte switching high to output valid 60 60 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . 3. to be considered only if the reset pulse is given while the memory is in erase or program mode. table 14b. read ac characteristics (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) 15/34 M29W400t, M29W400b
ai02092 tavav tavqv taxqx telqx tehqx tglqv tglqx tghqx valid a0-a17/ a1 e g dq0-dq7/ dq8-dq15 telqv valid address valid and chip enable output enable data valid byte tblqz telbl/telbh tehqz tghqz tbhqv figure 6. read mode ac waveforms note: write enable (w) = high. 16/34 M29W400t, M29W400b
symbol alt parameter M29W400t / M29W400b unit -90 -100 v cc = 3.0v to 3.6v c l = 30pf v cc = 2.7v to 3.6v c l = 30pf min max min max t avav t wc address valid to next address valid 90 100 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 45 50 ns t dvwh t ds input valid to write enable high 45 50 ns t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whwl t wph write enable high to write enable low 30 30 ns t avwl t as address valid to write enable low 0 0 ns t wlax t ah write enable low to address transition 45 50 ns t ghwl output enable high to write enable low 0 0 ns t vchel t vcs v cc high to chip enable low 50 50 m s t whgl t oeh write enable high to output enable low 0 0 ns t phphh (1,2) t vidr rp rise time to v id 500 500 ns t plpx t rp rp pulse width 500 500 ns t whrl (1) t busy program erase valid to rb delay 90 90 ns t phwl (1) t rsp rp high to write enable low 4 4 m s notes: 1. sample only, not 100% tested. 2. this timing is for temporary block unprotection operation. table 15a. write ac characteristics, write enable controlled (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) program (pg) instruction. this instruction uses four write cycles. both for byte-wide configuration and for word-wide configuration. the program command a0h is written to address aaaah in the byte-wide configuration or to address 5555h in the word-wide configurationon the third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of w or e and the data to be written on the rising edge and starts the p/e.c. read operations output the status register bits after the programming has started. memory programming is made only by writing '0' in place of '1'. statusbits dq6 and dq7 determine if program- ming is on-going and dq5 allows verification of any possible error. programming at an address not in blocks being erased is also possible during erase suspend. in this case, dq2 will toggle at the ad- dress being programmed. 17/34 M29W400t, M29W400b
symbol alt parameter M29W400t / M29W400b unit -120 -150 v cc = 2.7v to 3.6v v cc = 2.7v to 3.6v min max min max t avav t wc address valid to next address valid 120 150 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 50 65 ns t dvwh t ds input valid to write enable high 50 65 ns t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whwl t wph write enable high to write enable low 30 35 ns t avwl t as address valid to write enable low 0 0 ns t wlax t ah write enable low to address transition 50 65 ns t ghwl output enable high to write enable low 0 0 ns t vchel t vcs v cc high to chip enable low 50 50 m s t whgl t oeh write enable high to output enable low 0 0 ns t phphh (1,2) t vidr rp rise time to v id 500 500 ns t plpx t rp rp pulse width 500 500 ns t whrl (1) t busy program erase valid to rb delay 90 90 ns t phwl (1) t rsp rp high to write enable low 4 4 m s notes: 1. sample only, not 100% tested. 2. this timing is for temporary block unprotection operation. table 15b. write ac characteristics, write enable controlled (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) block erase (be) instruction . this instruction uses a minimum of six write cycles. the erase set-up command 80h is written to address aaaah in the byte-wide configuration or address 5555h in the word-wide configurationon third cycle after the two coded cycles. the block erase confirm com- mand 30h is similarly written on the sixth cycle after another two coded cycles. during the input of the second command an address within the blockto be erased is given and latched into the memory. addi- tional block erase confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further coded cy- cles. the erase will start after the erase timeout period (see erase timer bit dq3 description). thus, additional erase confirm commands for other blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the internal timer can be monitored through the level of dq3, if dq3 is '0' the block erase command has been given and the timeout is running, if dq3 is '1', the timeout has expired and the p/e.c. is erasing the block(s). if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to read array. it is not necessary to program the block with 00h as the p/e.c. will do this automatically before to erasing to ffh. read operations after the sixth rising edge of w or e output the status register status bits. 18/34 M29W400t, M29W400b
ai01869c e g w a0-a17/ a1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl figure 7. write ac waveforms, w controlled note: address are latched on the falling edge of w, data is latched on the rising edge of w. during the executionof the erase by the p/e.c.,the memory accepts only the erase suspend es and read/reset rd instructions. data polling bit dq7 returns '0' while the erasure is in progress and '1' when it has completed. the toggle bit dq2 and dq6 toggle during the erase operation. they stop when erase is completed. after completion the status register bit dq5 returns'1' if there has been an erase failure. in such a situation, the toggle bit dq2 can be used to determine which block is not correctly erased. in the case of erase failure, a read/reset rd instruction is necessary in order to reset the p/e.c. chip erase(ce) instruction. this instructionuses six write cycles. the erase set-up command 80h is written to address aaaah in the byte-wide con- figuration or the address 5555h in the word-wide configurationon the third cycle after the two coded cycles. the chip erase confirm command 10h is similarly written on the sixth cycle after another two coded cycles. if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to read array. it is not necessaryto programthe array with 00h first as the p/e.c. will automaticallydo this before erasing it to ffh. read operations after the sixth rising edge of w or e output the status register bits. during the execution of the erase by the p/e.c., data polling bit dq7 returns '0', then '1' on completion. the toggle bits dq2 and dq6 toggle during erase operation and stop when erase is completed. after completion the status register bit dq5 returns '1' if there has been an erase failure. 19/34 M29W400t, M29W400b
symbol alt parameter M29W400t / M29W400b unit -90 -100 v cc = 3.0v to 3.6v c l = 30pf v cc = 2.7v to 3.6v c l = 30pf min max min max t avav t wc address valid to next address valid 90 100 ns t wlel t ws write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 45 50 ns t dveh t ds input valid to chip enable high 45 50 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehwh t wh chip enable high to write enable high 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t avel t as address valid to chip enable low 0 0 ns t elax t ah chip enable low to address transition 45 50 ns t ghel output enable high chip enable low 0 0 ns t vchwl t vcs v cc high to write enable low 50 50 m s t ehgl t oeh chip enable high to output enable low 0 0 ns t phphh (1,2) t vidr rp rise time to v id 500 500 ns t plpx t rp rp pulse width 500 500 ns t ehrl (1) t busy program erase valid to rb delay 90 90 ns t phwl (1) t rsp rp high to write enable low 4 4 m s notes: 1. sample only, not 100% tested. 2. this timing is for temporary block unprotection operation. table 16a. write ac characteristics, chip enable controlled (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) erase suspend (es) instruction. the block erase operation may be suspendedby this instruc- tion which consists of writing the command b0h without any specific address. no coded cycles are required. it permits reading of data from another block and programming in another block while an erase operation is in progress. erase suspend is accepted only during the block erase instruction execution. writing this command during erase timeout will, in addition to suspending the erase, terminate the timeout. the toggle bit dq6 stops toggling when the p/e.c. is suspended.the toggle bits will stop toggling between0.1 m s and 15 m s after the erase suspend (es) command has been writ- ten. the device will then automatically be set to read memory array mode. when erase is sus- pended, a read from blocks being erased will output dq2 toggling and dq6 at '1'. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume er and the program pg instruc- tions. a program operation can be initiated during erase suspend in one of the blocks not being erased. it will result in both dq2 and dq6 toggling when the data is being programmed. aread/reset command will definitively abort erasure and result in invalid data in the blocks being erased. 20/34 M29W400t, M29W400b
symbol alt parameter M29W400t / M29W400b unit -120 -150 v cc = 2.7v to 3.6v v cc = 2.7v to 3.6v min max min max t avav t wc address valid to next address valid 120 150 ns t wlel t ws write enable low to chip enable low 0 0 ns t eleh t cp chip enable low to chip enable high 50 50 ns t dveh t ds input valid to chip enable high 50 50 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehwh t wh chip enable high to write enable high 0 0 ns t ehel t cph chip enable high to chip enable low 30 35 ns t avel t as address valid to chip enable low 0 0 ns t elax t ah chip enable low to address transition 50 50 ns t ghel output enable high chip enable low 0 0 ns t vchwl t vcs v cc high to write enable low 50 50 m s t ehgl t oeh chip enable high to output enable low 0 0 ns t phphh (1,2) t vidr rp rise time to v id 500 500 ns t plpx t rp rp pulse width 500 500 ns t ehrl (1) t busy program erase valid to rb delay 90 90 ns t phwl (1) t rsp rp high to write enable low 4 4 m s notes: 1. sample only, not 100% tested. 2. this timing is for temporary block unprotection operation. table 16b. write ac characteristics, chip enable controlled (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) erase resume (er) instruction. if an erase sus- pend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles. power supply power up the memory command interfaceis reset on power up to read array. either e or w must be tied to v ih during power up to allow maximum security and the possibility to write a command on the first rising edge of e and w. any write cycle initiation is blocked when vcc is below v lko . supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v cc rail decoupled with a 0.1 m f capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry the v cc pro- gram and erase currents required. 21/34 M29W400t, M29W400b
ai01870c e g w a0-a17/ a1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl figure 8. write ac waveforms, e controlled note: address are latched on the falling edge of e, data is latched on the rising edge of e. ai02091 rb w rp tplpx tphwl tplyh tphphh e tphel figure 9. read and write ac characteristics, rp related 22/34 M29W400t, M29W400b
sym- bol parameter M29W400t / M29W400b unit -90 -100 v cc = 3.0v to 3.6v c l = 30pf v cc = 2.7v to 3.6v c l = 30pf min max min max t whq7v write enable high to dq7 valid (program, w controlled) 10 2400 10 2400 ms write enable high to dq7 valid (chip erase, w controlled) 1.0 30 1.0 30 sec t ehq7v chip enable high to dq7 valid (program, e controlled) 10 2400 10 2400 m s chip enable high to dq7 valid (chip erase, e controlled) 1.0 30 1.0 30 sec t q7vqv q7 valid to output valid (data polling) 35 40 ns t whqv write enable high to output valid (program) 10 2400 10 2400 m s write enable high to output valid (chip erase) 1.0 30 1.0 30 sec t ehqv chip enable high to output valid (program) 10 2400 10 2400 m s chip enable high to output valid (chip erase) 1.0 30 1.0 30 sec note: 1. all other timings are defined in read ac characteristics table. table 17a. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) sym- bol parameter M29W400t / M29W400b unit -120 -150 v cc = 2.7v to 3.6v v cc = 2.7v to 3.6v min max min max t whq7v write enable high to dq7 valid (program, w controlled) 10 2400 10 2400 ms write enable high to dq7 valid (chip erase, w controlled) 1.0 30 1.0 30 sec t ehq7v chip enable high to dq7 valid (program, e controlled) 10 2400 10 2400 m s chip enable high to dq7 valid (chip erase, e controlled) 1.0 30 1.0 30 sec t q7vqv q7 valid to output valid (data polling) 50 55 ns t whqv write enable high to output valid (program) 10 2400 10 2400 m s write enable high to output valid (chip erase) 1.0 30 1.0 30 sec t ehqv chip enable high to output valid (program) 10 2400 10 2400 m s chip enable high to output valid (chip erase) 1.0 30 1.0 30 sec note: 1. all other timings are defined in read ac characteristics table. table 17b. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c, 20 to 85 c or 40 to 85 c) 23/34 M29W400t, M29W400b
ai01872b e g w a0-a17/ a1 dq7 ignore valid dq0-dq6/ dq8-dq15 address (within blocks) data output valid tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv figure 10. data polling dq7 ac waveforms 24/34 M29W400t, M29W400b
read dq5 & dq7 at valid address start read dq7 fail pass ai01369 dq7 = data yes no yes no dq5 =1 dq7 = data yes no figure 11. data polling flowchart read dq2, dq5 & dq6 start read dq2, dq6 fail pass ai01873 dq2, dq6 = toggle no no yes yes dq5 =1 no yes dq2, dq6 = toggle figure 12. data toggle flowchart parameter M29W400t / M29W400b unit min typ typical after 100k w/e cycles chip erase (preprogrammed) 1.5 1.7 sec chip erase 6.7 7.0 sec boot block erase 0.7 sec parameter block erase 0.6 sec main block (32kb) erase 0.9 sec main block (64kb) erase 1.4 sec chip program (byte) 7.5 7.5 sec byte program 10 10 m s word program 16 16 m s program/erase cycles (per block) 100,000 cycles table 18. program, erase times and program, erase endurance cycles (t a = 0 to 70 c; v cc = 2.7v to 3.6v) 25/34 M29W400t, M29W400b
ai01874b e g w a0-a17/ a1 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5,dq7/ dq8-dq15 figure 13. data toggle dq6, dq2 ac waveforms note: all other timings are as a normal read cycle. 26/34 M29W400t, M29W400b
block address on a12-a17 ai01875e g, a9 = v id , e=v il n=0 wait 4 m s wait 100 m s w=v il w=v ih e, g = v ih verify block protection a0, a6 = v il ;a1=v ih ;a9=v id a12-a17 identify block a9 = v ih ++n =25 start fail pass yes no data = 01h yes no a9 = v ih set-up protect verify w=v ih wait 4 m s wait 60ns g=v il verify block protect status e=v il figure 14. block protection flowchart 27/34 M29W400t, M29W400b
protect all blocks ai01876c data e, g, a9 = v id a12, a15 = v ih wait 4 m s w=v ih e, g = v ih wait 10ms = 00h next block w=v il ++n = 1000 start a9 = v ih yes yes no a9 = v ih no last blk. yes no n=0 set-up unprotect verify w=v ih e, a0 = v il ; a1, a6 = v ih ;a9=v id a12-a17 identify block wait 4 m s wait 60ns g=v il verify block protect status fail pass figure 15. all blocks unprotecting flowchart 28/34 M29W400t, M29W400b
ordering information scheme M29W400t and M29W400b are replaced respectively by the new version M29W400bt and M29W400bb devices are shipped from the factory with the memory content erased (to ffh). for a list of available options(speed, package,etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. operating voltage w 2.7v to 3.6v array matrix t top boot b bottom boot speed -90 90ns -100 100ns -120 120ns -150 150ns package n tsop48 12 x 20mm m so44 za fbga48 0.8mm ball pitch option r reverse pinout tr tape & reel packing temp. range 1 0 to 70 c 5 20 to 85 c 6 40 to 85 c example: M29W400t -90 n 1 tr 29/34 M29W400t, M29W400b
tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 11.90 12.10 0.469 0.476 e 0.50 - - 0.020 - - l 0.50 0.70 0.020 0.028 a 0 5 0 5 n48 48 cp 0.10 0.004 drawing is not to scale. tsop48 normal pinout - 48 lead plastic thin small outline, 12 x 20mm 30/34 M29W400t, M29W400b
tsop-b d1 e 1n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 11.90 12.10 0.469 0.476 e 0.50 0.020 l 0.50 0.70 0.020 0.028 a 0 5 0 5 n48 48 cp 0.10 0.004 drawing is not to scale. tsop48 reverse pinout - 48 lead plastic thin small outline, 12 x 20mm 31/34 M29W400t, M29W400b
so-b e n cp b e a2 d c l a1 a h a 1 symb mm inches typ min max typ min max a 2.42 2.62 0.095 0.103 a1 0.22 0.23 0.009 0.010 a2 2.25 2.35 0.089 0.093 b 0.50 0.020 c 0.10 0.25 0.004 0.010 d 28.10 28.30 1.106 1.114 e 13.20 13.40 0.520 0.528 e 1.27 0.050 h 15.90 16.10 0.626 0.634 l 0.80 0.031 a 3 3 n44 44 cp 0.10 0.004 drawing is not to scale. so44 - 44 lead plastic small outline, 525 mils body width 32/34 M29W400t, M29W400b
symb mm inches typ min max typ min max a 1.250 1.150 1.350 0.049 0.045 0.053 a1 0.300 0.250 0.350 0.012 0.010 0.014 a2 0.950 0.037 b 0.400 0.350 0.450 0.016 0.014 0.018 ddd 0.150 0.006 d 9.000 8.800 9.200 0.354 0.346 0.362 d1 5.600 0.220 e 0.800 0.031 e 6.000 5.800 6.200 0.236 0.228 0.244 e1 4.000 0.157 sd 0.400 0.016 se 0.400 0.016 drawing is not to scale. fbga48 - 48 balls (8 x 6) fine pitch ball grid array, 0.80mm pitch e1 e d1 d eb sd se a2 a1 a bga-z00 ddd ball oa1o 33/34 M29W400t, M29W400b
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 34/34 M29W400t, M29W400b

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